1. Field of the Invention
This invention generally relates to the design of integrated circuits, and more specifically, the invention relates to an automated way of accessing internal signals or ports in the design hierarchy of an integrated circuit design.
2. Background Art
The process of creating Very-Large-Scale Integrated (VLSI) circuit designs typically includes a structured sequence of steps. In an initial step, a VLSI circuit designer creates a computerized representation of a VLSI circuit design using a computerized tool. In the ensuing steps, the designer generates a series of subsequent representations using specialized tools including synthesis tools, optimization tools, and place-and-route tools. The designer might also generate a new representation manually using a computerized editing tool.
In general, each representation in the series describes the design at a different level of abstraction. It is common for the initial representation to describe the design at a high level of abstraction, and for each subsequent representation to describe the design at a respective lower level of abstraction. For example, the initial representation may describe the design at the Register-Transfer Level (RTL), a subsequent representation may describe the design at the gate-level, and a subsequent representation from that may describe the design at the transistor-level. The process culminates with the generation of a database containing geometric detail of masks that will be used to fabricate the design.
A circuit design representation describes a design as a set of basic components that are connected together. Due to the size and complexity of VLSI circuit designs, it is a common practice for the designer to group components together in subsets called module definitions (or modules). A module defines an arrangement of components and other modules, and can be instantiated more than once in a representation. That is, the designer creates a module once to define an arrangement of elements, and uses instances of that module to represent specific portions of the design. Many Hardware Description Languages (HDLs) support this hierarchical manner of design description. Designs are written as a set of module definitions. Computerized tools that read such designs can construct the full hierarchical representation of the design from the module definitions. In the full hierarchical representation, each element of the design has a unique representation.
Once the circuit design is completed, the design is verified to ensure that the design adheres to certain rules and to verify that particular design aspects such as functional behaviors have been preserved from representation to representation. Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limits. In order to exercise the complex designs, various and comprehensive scenarios will be depicted in the form of test-cases. These test-cases usually range from hundreds to many thousands depending on the complexity of the design. These testcases which will be generated by the user are called directed testcases.
While generating these test-cases, access is usually needed to the internal ports or signals to verify the designs. Especially while doing the connectivity tests, the internal ports are used more often. In general, when the internal ports are used in the testcases, the complete hierarchy path is needed from the top module to the lower level module of these ports from the top design for test.
When the design is small, it may be relatively simple to provide the complete design path. But in today's world, as the design size increases and there are more blocks inside the design, the hierarchy path is long and very tedious to write in each and every testcases. The user has to remember the complete path. The process of writing the complete hierarchy path into each testcase is not automated, needs a lot of manual interaction, and is a very time consuming job. Also, if the block is realigned during floor planning or during the design stage, then the testcases needs to be remodified, which consumes even more time. As the time to market is very critical, the verification cycle time of the design is very critical and this leads to more time and manpower to finish this task.
Hence there is a need for the automation of the hierarchical path detection which will reduce the time and manual interaction and helps in finishing the verification task faster.